Method and apparatus for incremntally optimizing a circuit design
US6026220A · kind A · utility
29Cited by
35References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1996 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Nov 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for incrementally optimizing a circuit design. The present invention provides an iterative EDA process that only requires the optimization, placement and routing of the actual changes made during a each design iteration, and leaves the remainder of the circuit design in a fixed state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.