System for combinational equivalence checking
US6026222A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1997 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Dec 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system, computer program product, and method for solving a combinational logic verification problem with respect to two combinational circuits includes Boolean SAT checking integrated with binary decision diagrams (BDD) use. A fanout partition of a miter circuit formed from the two combinational circuits is reduced to BDD form, while the fanin partition is represented by SAT clauses. As SAT solutions are evaluated, variables in the cutset between the fanout and fanin partitions are assigned values. In a preferred embodiment, each assignment to a cutset variable is checked against an onset of the BDD prior to continuing with SAT solution seeking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.