Multi-virtual DMA channels, multi-bandwidth groups, host based cellification and reassembly, and asynchronous transfer mode network interface
US6026443A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1992 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Dec 22, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control memory is provided for storing the control and state information of a number of virtual direct memory access (DMA) channels. A control memory arbiter and a control memory data bus are also provided to arbitrate accesses to the control memory to facilitate asynchronous transmit and receive. Separate areas in the control memory are provided for storing the control and state information of the transmit DMAs, and the receive DMAs. Additionally, descriptive information about the transmit/receive data ring and its descriptor, the data packet being transferred and its cells are also stored for the transmit and receive DMAs. The control memory is also used to stored a programmable bandwidth group (BWG) table comprising a plurality of BWG index entries for bandwidth selection. A Segmentation And Reassembly (SAR) module which cellifies transmit packets and reassembly receive packets on the host computer is also provided for segmenting transmit packets into transmit cells for transmission, and reassembling receive cells into receive packets. Two series of FIFOs are provided for staging the transmit and receive cell payloads. Lastly, complement to the SAR module, a media cell manager…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.