Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system
US6026455A · kind A · utility
9Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1994 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Feb 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.