Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency
US6026460A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1996 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | May 10, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge includes a bus activity monitor for monitoring bus cycles on a first bus, an inbound posting buffer, and a control logic. The control logic indicates whether to grant control of the first bus to a first processor on the first bus based on whether the inbound posting buffer is empty, and also controls disabling of posting to the inbound posting buffer. The control logic disables inbound posting responsive to both the first processor being backed off the system bus a predetermined number of times and the inbound posting buffer being empty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.