Parity check circuit
US6027243A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 1998 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Mar 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parity check circuit for inspecting a piece of binary information having n bits including a parity bit provided with n EXCLUSIVE-OR circuits for receiving each bit of the piece of binary information, at least one stage composed of EXCLUSIVE-OR circuits having the number of a half of the previous stage until the number of the EXCLUSIVE-OR circuits reaches one, and an error detector, further including at least one data register circuit intervening between each of the stages and for receiving a set of data from the previous stage, forwarding the previous set of data which has been registered therein toward the next stage, and registering the set of data newly delivered to the stage, in response to a check signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.