Semiconductor wafer testing apparatus with a combined wafer alignment/wafer recognition station
US6027301A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1997 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Sep 26, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/14
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor wafer testing apparatus has a work table on which a carrier containing semiconductor wafers to be checked is placed. The work table is equipped for combined wafer alignment and wafer code recognition while the wafers remain in their carrier in one position on the work table. The alignment is accomplished with a wafer flat zone aligner which has a pair of roller pins each coming in contact with circumferences of the wafers being stacked in the carrier through an open lower part of the carrier and an opening in the table. The wafer code recognition is accomplished with an optical character recognizer that moves up and down and forward and backward with respect to the carrier, and interposes between the wafers in the carrier so as to read out codes which are on each wafer. This combined automated work station helps prevent contamination of the wafers by an operator or by unnecessary handling of the wafers, and also reduces cycle time for the entire inspection process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.