Method for evaluating a semiconductor device
US6027949A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 1997 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | May 1, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A P-type silicon substrate (4) and an N-type diffusion layer region (6) are connected to aluminum electrodes (5 and 7), respectively. Respective sections of the P-type silicon substrate (4) and the N-type diffusion layer region (6) are exposed. The aluminum electrode (5) connected to the P-type silicon substrate (4) and a platinum electrode (1) are connected in common to a cathode of a DC power supply (3a) and the aluminum electrode (7) connected to the N-type diffusion layer region (6) is connected to an anode of the DC power supply (3a). A sample for evaluation is thus provided. Of this sample, the exposed sections of the P-type silicon substrate (4) and the N-type diffusion layer region (6) are dipped into a mixture (2) of hydrofluoric acid and alcohol, and a voltage not lower than a critical voltage is applied thereto by the DC power supply (3a). Thus, an evaluation of a form of a diffusion layer region in a semiconductor device is achieved with excellent reproducibility.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.