Semiconductor structures and packaging methods
US6028347A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1996 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Dec 10, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure having: semiconductor devices formed in an inner region of a semiconductor chip; a seal ring formed in the chip and disposed about the inner region; and, a plurality of trenches formed along a surface of the chip. The trenches are disposed in a corner region of the chip. A portion of the seal ring is disposed between the trenches and the inner region of the chip. The trenches are disposed along axes oblique to outer edges of the chip. A method is provided for encapsulating a semiconductor chip. The method includes the steps of: providing a semiconductor chip having active semiconductor devices in an inner region of the semiconductor chip and a seal ring in the chip about the inner region; and, forming a plurality of trenches in the chip, a portion of the seal ring being formed between the trenches and the inner region of the chip. A cover is formed having bottom portions in the trenches and on the passivation layer. In particular, the cover is formed by flowing plastic material over the passivation layer and into the trenches to fill such trenches with such plastic material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.