Integrated circuit I/O buffer having pull-up to voltages greater than transistor tolerance
US6028449A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 1997 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Aug 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An integrated circuit having a DC current test function operates at a core supply voltage and interfaces at an input-output (I/O) supply voltage. The I/O supply voltage is greater than the core supply voltage. The integrated circuit includes a buffer, a voltage level shifting circuit and a pull-up circuit. The buffer is coupled between a core terminal and a pad terminal. The pad terminal has a voltage swing which is substantially equal to the I/O supply voltage. The voltage level shifting circuit has a test signal input with a voltage swing substantially equal to the core supply voltage and a test signal output with a voltage swing from the I/O supply voltage to a selected bias voltage. The pull-up circuit is coupled to the pad terminal and has a control terminal coupled to the test signal output. The pull-up circuit pulls the pad terminal toward the I/O supply voltage during normal operation and selectively isolates the pad terminal from the I/O supply voltage as a function of the test signal during a DC current test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.