Volatile memory and embedded dynamic random access memory
US6028805A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 1998 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Nov 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a structure in which a refresh region to be actually refreshed can be set on an outside of a DRAM. A refresh control register (21) is provided to store a refresh control bit which is sent from the outside and indicates the region to be refreshed. A refresh address deciding circuit (22) is provided to compare a content (RCB) stored in the refresh control register (21) with a refresh address (RAi) output from a refresh address generating circuit (11). An internal timing control circuit (5A) stops operations of a row decoder (3) and a sense amplifier (4) according to a result of a decision made by the refresh address deciding circuit (22).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.