Delay lock loop with transition recycling for clock recovery of NRZ run-length encoded serial data signals
US6028903A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1997 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Mar 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit uses a pair of variable delay lines to recover clock from a non-return to zero (NRZ) data stream. If an incoming clock transition occurs in the NRZ data, it is passed through one delay line to the output. If no incoming transition occurs, the transition at the output of the first delay line is recycled back through the second delay line. The outputs of the first and second delay lines are combined so that a transition occurs at every possible transition instant, regardless of whether a transition is present in the incoming data at the corresponding time. This permits the benefits of a delay locked loop to be achieved when using NRZ data. Applications of the clock recovery circuits to gigabit data communications systems are describe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.