Data processor with circuit for regulating instruction throughput while powered and method of operation
US6029006A · kind A · utility
45Cited by
11References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1996 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Dec 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor (10) incorporates instruction regulating or "throttling" circuitry (31) for limiting consumed power. A user visible register maintains an INTERVAL field by which instruction fetch from an instruction cache (14) is periodically delayed. This INTERVAL field may be adjusted to suit the power budget of the data processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.