Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers
US6029212A · kind A · utility
19Cited by
34References
4Claims
0Family size
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Key dates
| Filing date | Jan 13, 1998 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Jan 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.