Data processing system using a shared register bank and a plurality of processors
US6029242A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Oct 20, 1997 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Oct 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3889
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is provided for use in register-based CPUs for simultaneously processing data in a series of CPU register banks while concurrently loading and unloading data into additional register banks. The register banks then sequentially shared between arithmetic processors connected to the CPU datapath. Each register bank, after being loaded with data, is connected to a plurality of data processors in sequence and the data in each register bank is processed. The data is not moved between register banks within the datapath, except when it is loaded and unloaded from the datapath. The invention takes advantage of the shorter time required to move control signals, as compared with moving data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.