Minimum error algorithm/program
US6030154A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1998 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Jun 19, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T408/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for optimizing the drilling position of a multi-layer printed circuit board prior to drilling. Each board is x-rayed to determine location coordinates information of the inner layers of multi layer circuit board panels. An optimization process determines optimal locations for drilling. The board is then drilled according to the optimized coordinates. By minimizing misregistration between the drilled holes and inner layers of the multi layer semiconductor circuit board, the present invention reduces a significant cause of scrap to the circuit board industry as well as removing a major impediment to further increasing circuit density and wireability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.