Self-aligned copper interconnect architecture with enhanced copper diffusion barrier
US6030896A · kind A · utility
24Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 21, 1999 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Apr 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A via is formed in a semiconductor device using a self-aligned copper-based pillar to connect upper and lower copper interconnect layers separated by a dielectric. The lower interconnect layer is formed on an underlying layer. The copper-based via pillar is formed on the lower interconnect layer. The upper interconnect layer is formed to make electrical contact to the exposed upper surface of the via pillar. Conductive diffusion barrier material is formed on vertical sidewalls of the lower interconnect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.