Semiconductor device

US6031245A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Nalin Patel · Cambridge, GB
• Mark Leadbeater · Depden, GB
• Llewellyn John Cooper · Cambridge, GB

Key dates

• Filing date: Dec 11, 1998
• Grant date: Feb 29, 2000
• Expiry date: Dec 11, 2018

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B82Y10/00
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A semiconductor device is presented which exhibits both interband and intraband tunnelling. The device comprises two active layers (21, 23) which are sandwiched between two barrier layers (3, 5). These layers are located between first and second terminals (7, 9). The active layers (21, 23) are chosen such that the conduction band edge (27) of the first active layer (21) having a lower energy than the valence band edge (25) of the second active layer (23); PA1 the first active layer (21) having a first confined conduction band energy level (29) with an energy higher than that of the conduction band edge (27) of the first active layer (21); PA1 the second active layer (23) having a first confined valence band energy level (33) with an energy lower than that of the valence band edge (25) of the second active layer (23); PA2 wherein the first confined valence band energy level (33) and the first confined conduction band energy level (29) are located such that the device can exhibit both intraband and interband tunnelling.