Clock synchronizing circuit with power save mode
US6031402A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Nov 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock synchronizing circuit provides reduced power consumption. A first phase comparator compares an external clock signal delayed for a predetermined time with a feedback clock signal to detect their phase error, and a second phase comparator compares an external clock signal with a feedback clock signal delayed for a predetermined time to detect their phase error. A charge pump changes a charge amount depending on phase error detecting signals from the first and second phase error comparators, and a phase compensator compensates the phase of the external clock signal depending on the charge amount from the charge pump. A controller controls the overall system or some portion thereof to be converted to a power save mode if the phase of the external clock signal is synchronized with that of the feedback clock signal by the phase compensator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.