Pull-up and pull-down circuits
US6031403A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1996 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Nov 13, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to the preferred embodiment of the present invention pull-up/pull-down circuits are provided that use transistors with different threshold voltages to assure power-up to the correct predetermined state. These circuits have the ability to hold a node up or down while drawing very little DC current. In one embodiment a pull-up/pull-down circuit is provided that powers up to a first state with the pull-up node high and the pull-down node low, and that can be toggled from one state to another. A second embodiment provides a pull-up or pull-down circuit that powers up to the desired state and can be disabled by pulling the pull-up node low or pulling the pull-down node high. The circuits remain disabled until the power to the circuit is cycled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.