Semiconductor integrated circuit using direct coupled FET logic configuration for low power consumption
US6031413A · kind A · utility
17Cited by
1References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 9, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Jun 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/242
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A semiconductor integrated circuit is constructed with multiple stages of circuit blocks connected in vertical series between a first power supply line and a second power supply line. At least one of the circuit blocks is provided with a load unit connected in parallel therewith so that each circuit block consumes an approximately equal amount of current. This makes it possible to generate a stable intermediate voltage and suppress increases in current consumption and circuit area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.