Method and apparatus for implementing a pipelined A/D converter with inter-stage amplifiers having no common mode feedback circuitry
US6031480A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Nov 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/249
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipelined analog-to-digital converter is disclosed having a plurality of sample and hold converter stages, each having an interstage amplifier (28) associated therewith. This is a differential amplifier that is implemented without common-mode feedback. The sample and hold stage operates on a reset phase and a gain/DAC phase, wherein the output of the reconstructive DAC is summed with the input to the amplifier (28). A differential input amplifier (60) has the inputs thereof set to common-mode input voltage with a feedback capacitor biased to a common-mode output bias point. During the gain/DAC phase, the bias input is removed and the feedback capacitor connected across the input/output of the amplifier (60). This effectively establishes the common-mode bias points for use by the amplifier (60) during the gain/DAC phase. Further, the differential inputs of the amplifier (60) are connected to one side of respective sampling capacitors, the other side thereof connected through a respective switch to the differential inputs. During the reset phase the input voltage is sampled onto the capacitors and, during the gain/DAC phase, the gates of the capacitors are connected together to rem…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.