Low latency shared memory switch architecture
US6031842A · kind A · utility
86Cited by
28References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.