High-speed binary synchronous counter
US6031887A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1997 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Jul 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first input, a test carry signal as a second input, and a control input, the switchable device being capable of providing one of its inputs as an output, the control input capable of controlling selection of the output which is a carry signal. The subcounter also includes an n/k-bit counter, the n/k-bit counter receiving the carry signal and providing n/k output bits, and logic for combining the n/k-bits output from the n/k bit counter with the carry-out signal from an adjacent subcounter to provide an output that is a carry-out signal from the subcounter. The logic introducing a single gate delay between the carry-out signal from the adjacent subcounter and the carry-out signal from the subcounter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.