Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory
US6032230A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1998 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Dec 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Inconsistencies between cache and memory in a memory system operating in a computer are traced and corrected. A cache entry is checked against a counterpart memory entry to trace inconsistencies between the cache entry and the memory entry and to correct the cache entry. A page table entry in memory with a zero mapping mark is checked against a counterpart page entry in a translation lookaside buffer. Inconsistencies between the page table entry with a zero mapping mark and the existence of a counterpart page entry in the translation lookaside buffer is traced. The inconsistency is corrected by deleting the counterpart page entry in the translation lookaside buffer. Address mapping is checked comparing a page entry in the translation lookaside buffer against a counterpart page table entry in the memory. Inconsistencies between the page entry and the page table entry are traced and corrected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.