Network of triacs with gates referenced with respect to a common opposite face electrode
US6034381A · kind A · utility
22Cited by
4References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 9, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Jun 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/80
Abstract
The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.