High speed biCMOS gate power for power MOSFETs incorporating improved injection immunity
US6034413A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1998 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Nov 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages. The circuit can tolerate negative voltages up to approximately two diode drops on its output and gate drive terminals because (a) when transistor Q2 is conducting it is effectively configured as an NPN diode and the collector cannot sustain a voltage less than one base-emitter drop above …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.