Level shift circuit
US6034549A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Oct 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shift circuit consisting MOSFETs is provided which comprises at least two bias voltage supply circuits and a driver circuit cascaded between input and output terminals of the level shift circuit. The first stage of the bias voltage supply circuits receives an input voltage and the last stage thereof supplies a level-shifted voltage to the driver circuit. The driver circuit includes N- and P-channel transistors. Gates of the transistors of the driver circuit receive the level-shifted voltage from the bias voltage supply circuits and the input voltage, respectively. Sources of the transistors of the driver circuit are commonly connected to the output terminal to provide an output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.