Semiconductor memory device for a rapid random access
US6034911A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1996 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Oct 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory device includes a plurality of memory blocks, a memory block selecting circuit and a column decoder. Each memory block comprise a memory cell array including a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells, and a peripheral circuit including sense amplifiers which amplify data read out onto bit line pairs when a memory block select signal for a particular memory block is active to connect all memory cells contained in one row with associated bit line pairs. An access control circuit changes a block address and a column address while maintaining a row address unchanged, thus performing a rapid random access of memory cells contained in a common row over the memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.