Method for performing functional comparison of combinational circuits
US6035107A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Aug 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A verification technique which is specifically adapted for formally comparing large combinational circuits with some structural similarities. The approach combines the application of Binary Decision Diagrams (BDDs) with circuit graph hashing, automatic insertion of multiple cut frontiers, and a controlled elimination of false negative verification results caused by the cuts. Multiple BDDs are computed for the internal nets of the circuit, originating from the cut frontiers, and the BDD propagation is prioritized by size and discontinued once a given limit is exceeded. The resulting verification engine is reliably accurate and efficient for a wide variety of practical hardware designs ranging from identical circuits to designs with very few similarities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.