Multi-port SRAM access control using time division multiplexed arbitration
US6035360A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Oct 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface for multi-port access to a memory unit, such as a static random-access memory (SRAM) device. The memory interface, which is generally adapted for a local area network (LAN) forwarding engine, provides single port read/write access to SRAM device, and arbitrates requests from the access interfaces to allocate bandwidth of the SRAM device among the requests. One embodiment allocates at least 50% of the bandwidth to a peripheral component interface (PCI) bus target interface and a PCI bus master interface, collectively. The arbitration logic may include a plurality of bandwidth control registers associated with respective access interfaces used to determine a permitted amount of bandwidth that an access interface is to have, wherein a request from an access interface is masked based on a value in its associated bandwidth control register. Arbitration can further allocate bandwidth using time division multiplexing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.