Solid state disk drive address generator with multiplier circuit
US6035384A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1996 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | May 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a block size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.