Scheduling instructions with different latencies
US6035389A · kind A · utility
63Cited by
4References
47Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1998 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Aug 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a clock to produce pulses and an electronic hardware structure having a plurality of rows and one or more ports. Each row is adapted to record a separate latency vector written through one of the ports. The latency vector recorded therein is responsive to the clock. A method of dispatching instructions in a processor includes updating a plurality of expected latencies to a portion of rows of a register latency table, and decreasing the expected latencies remaining in other of the rows in response to a clock pulse. The rows of the portion correspond to particular registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.