Method and apparatus for fault on use data error handling
US6035436A · kind A · utility
14Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for handling different of types of data bit errors in a computer system. In one embodiment, the method comprises the step of storing a data line in a first storage location. The method also includes the step of retrieving the data line from the first storage location. Data bit errors in the data line are detected and the data line is marked as containing a data bit error and stored in a storage location if the data line is not to be used immediately by a requesting process; otherwise error handling is performed by halting the requesting process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.