Metal-encapsulated polysilicon gate and interconnect
US6037233A · kind A · utility
13Cited by
21References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1998 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | Apr 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0223
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.