Error compensator circuits used in color balancing with time multiplexed voltage signals for a flat panel display unit
US6037918A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1998 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | Mar 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0666
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for time multiplexing a voltage signal for controlling the color balance of a flat panel display. Within an FED screen, a matrix of rows and columns is provided and emitters are situated within each row-column intersection. Row drivers are sequentially activated during "row on-time windows" and corresponding individual gray scale information (voltages) are driven by the column drivers. When the proper voltage is applied across the cathode and anode of the emitters, electrons are released toward a phosphor spot, e.g., red, green, blue, causing illumination. Within each column driver, selection circuitry is provided for driving a first voltage data during a first part of the row on-time window and a second voltage data during a second part of the row on-time window. The lengths of the first part and second part of each row on-time window can be adjusted, for a given color, to adjust the color balance with respect to that color. In one embodiment, two data translators or "error compensation circuits" are used to compensate for errors caused by dividing the first voltage data when obtaining the second voltage data. Considering consecutive frame pairs, a first error…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.