Bypass circuit for bypassing host computer which are connected to plurality of devices via two individual ports upon detecting lack of communication at both ports
US6038618A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 1997 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | Aug 8, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/437
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.