Interrupt control on SMM
US6038632A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1998 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | May 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an initialization operation of a system, an I/O trap SMI is issued to a CPU, and CPU state map information is stored in a predetermined area in an SM-RAM. When an interrupt control process occurs during the activation of an OS, the CPU state map information formed in the initialization operation is set in the CPU, and the CPU operation mode is changed to an original mode in which interrupts from various I/O devices are enabled. In the original mode of the CPU, parallel processing using an interrupt is executed. Initialization commands are sequentially issued to a plurality of devices such as a KBC, an HDD, and a display controller. The KBC, the HDD, and the display controller generate command completion interrupt signals upon completion of the command processes for their initialization operations. Next commands are sequentially issued to devices which have generated the command completion interrupt signals. A plurality of devices are initialized in accordance with the command completion interrupt signals from these devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.