Computer system with power management scheme for DRAM devices
US6038673A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1998 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | Nov 3, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system employs DRAM devices in a memory sub-system, which devices are assigned into particular pools corresponding to different power consumption states with a most-recently-accessed (MRA) device being assigned to an active pool and placed at the top of a stack structure. A LRA device in the active pool is evicted from the active pool and placed in a standby pool when the active pool is full and the processor accesses another device, which is not currently assigned to the active pool. A LRA device of the standby pool gets evicted into a nap pool upon one of two conditions: either a timeout occurs, or the standby and active pools are full and the processor accesses another device, which is not currently assigned to either the active or standby pools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.