Method of analyzing logic circuit test points, apparatus for analyzing logic circuit test points and semiconductor integrated circuit with test points
US6038691A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1998 |
| Grant date | Mar 14, 2000 |
| Priority date | — |
| Expiry date | Jan 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test point analyzing apparatus determines a distinction between capability and incapability of insertion of a test point and a circuit modifying way when a test point is capable of being inserted for each of the test point types to each of the signal lines in a semiconductor integrated circuit by using circuit information, a test point insertion library, and test point insertion. Then, test point indexes to test point candidates capable of being inserted are calculated, and test point candidates having a large testability are selected based on the indexes, and the selected test point candidates are registered in test point information. Such processing is repeated until a predetermined condition of completing the test point analysis process is realized. In the apparatus, a test point index calculation portion calculates test point index information including CRF (Cost Reduction Factor) of each signal line from circuit information, determines a predetermined number of test point candidates in order of the CRF, and calculates COP (Controllability Observability Procedure, hereinafter referred to as test cost) when each of the test point candidates is assumed to be inserted. By settin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.