Method of stacking chips with a removable connecting layer
US6040204A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1998 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Aug 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing chip stacks in which wafers are stacked one on top of the other. The wafer is provided with an adhesive foil on its bottom, and is subsequently cut into chips so that the adhesive foil remains intact and the chips adhering to the adhesive foil are stacked one on top of the other. A first layer of chips is reversibly attached to a baseplate, the adhesive foil is removed, the next layer of chips is attached to the bottom side of the chips already fastened to the baseplate, the adhesive foil is removed, and the last two steps are repeated until the desired number of chips is stacked one on top of the other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.