Bus driver circuit having adjustable rise and fall times
US6040724A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 13, 1996 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Sep 13, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bus driver circuit for high speed data transmission includes a plurality of delay blocks connected in series one to another which varies a rise and fall time of an input signal in order to shape an output waveform. Each block includes one or more delay elements for providing a predetermined delay period. A selector input is provided for each delay block such that one or more of the predetermined delay periods can be selected. Hence, the rise and fall time of the input signal can be varied depending upon which block or combination of blocks have been selected to shape the resultant waveform. An output circuit is also included which superimposes the input signal on the resultant output waveform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.