Flash memory leveling architecture having no external latch
US6040997A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1998 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Mar 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved flash memory system includes a flash array, internal buffer, and internal controller. When data is written from a source block to a destination block, the improved flash memory system temporarily holds this data inside the internal buffer within the flash memory system to save the overhead of sequentially transferring the data out of the flash system and then sequentially returning the data back to the system. Alternatively, the data can be read and concurrently programmed onto the destination block without being written into an internal latch. In use, this improved flash memory system simply transfers the data to be rewritten from the flash array either directly or to the internal buffer. This improved flash memory system locates a new address within this same flash array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.