Optimizing page size in mixed memory array using address multiplexing
US6041016A · kind A · utility
24Cited by
4References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1998 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Dec 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a method and apparatus for addressing a memory array. The memory array has N rows of memory devices with different page sizes. A memory address corresponding to one of the N rows of memory devices is generated. A device bank address is selected corresponding to a device size and a device page size of the one of the N rows of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.