Apparatus and method for analyzing passive circuits using reduced-order modeling of large linear subcircuits
US6041170A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1997 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Jul 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for generating and analyzing a reduced-order model of a linear circuit. The method and apparatus generates the symmetric multi-port transfer function of an RLC circuit. The invention employs a novel symmetric block-Lanczos-type procedure, termed SyMPVL for Symmetric Matrix Pade via Lanczos, to reduce original circuit matrices to a pair of banded symmetric matrices. When the circuit comprises only two of the three RLC components, the matrices are also positive definite. These matrices are typically much smaller than the original circuit matrices and determine a reduced-order model of the original multi-port transfer function of the circuit. The reduced transfer function represents a matrix-Pade approximation of the original multi-port matrix transfer function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.