Efficient decimation filtering
US6041339A · kind A · utility
66Cited by
15References
50Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0685
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decimation filtering circuit for performing a decimation operation with a decimation factor of M in a pipelined structure. A finite impulse response ("FIR") filtering of N taps for achieving a desired frequency response is designed to have an integral ratio of N/M. A total of N/M processing stages is connected in series to accumulate filtered data based on data samples of an input signal and predetermined FIR coefficients. Each of the N/M processing stages produces an accumulated output in every other M accumulations for M input data samples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.