Circuit and method for controlling memory depth
US6041388A · kind A · utility
4Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1997 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Feb 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array having a physical depth of 2N-bits (N being an integer) includes control and data bus logic configured to control read and/or write operation in the memory array and to select the depth of the memory array. The control logic may include upper and lower byte control circuitry and the depth of the array may be selected from a group consisting of xN-bits and 2xN-bits, x being an integer. The control and data bus logic may be implemented as metal options within the device to be selected during fabrication to achieve a desired array depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.