Array padding for higher memory throughput in the presence of dirty misses
US6041393A · kind A · utility
23Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 23, 1996 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Aug 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array padding technique is described that increases memory throughput in the presence of dirty misses. The technique pads arrays so that the starting addresses of arrays within a target loop are separated by P memory banks where P is a rounded integer equal to the number of memory banks divided by the number of arrays. The number of banks of separation can be incremented or decremented by 1 to also avoid path conflicts due to the sharing of buses in a typical hierarchical memory subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.