Fault tolerant memory system
US6041422A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 1997 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Oct 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant semiconductor memory system has a main memory (1) having a first plurality of individually addressable storage locations. The system additionally has means for storing the address of ones of the storage locations which are defective, substitute memory comprising a second plurality of individually addressable storage locations mapped to corresponding ones of the defective storage locations, and control means comprising a plurality of comparators (20, 21, 23) for comparing a received address signal with a respective one of the addresses of the defective storage locations, each comparator being directly coupled to a corresponding one of the substitute storage locations, wherein read and write access can be re-routed from a defective storage location to the corresponding substitute storage locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.