Error detection and correction code for data and check code fields
US6041430A · kind A · utility
118Cited by
14References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 3, 1997 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | Nov 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for detecting and correcting single bit errors, detecting double bit errors, and detecting multiple bit errors within a nibble of a data field comprising 135 data bits and 9 check bits. 9 check bits are generated based on 135 data bits. The 9 check bits are appended to the data bits and the cumulative data field is checked for errors. An error detection syndrome is generated that indicates whether an error has occurred and whether the error is correctable. Check bit generation and error detection syndrome generation is accomplished based on the ordering in an ECC code matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.